Multiplexer

library ieee;
use ieee.std_logic_1164.all;

entity plexer
port(
a,b,c,d,s1,s2: in bit;
y:out bit);
end plexer;

architecture multi of plexer is
begin
proc: process is
begin
if (s1='0' and s2='0') then y <= a;
else if (s1='0' and s2='1') then y <= b;
else if (s1='1' and s2='0') then y <= c;
else if (s1='1' and s2='1') then y <= d;
end if;
end process proc;
end multi;

entity sinyal is
port(
pa,pb,pc,pd,ps1,ps2:out bit);
end sinyal;

architecture sinyal of sinyal is
begin
pros: process is
begin
pa <= '0';
pb <= '1';
pc <='1';
pd <= '0';
ps1 <= '1';
ps2 <= '0';
end process pros;
end sinyal;